1. Field of the Invention
The present invention relates to a video display control unit. More specifically, it relates to a video display control unit which generates characters and/or graghic patterns on the basis of video information stored in a video memory thereby to display the characters and/or graphic patterns on a sequential scanning display unit.
2. Description of the Prior Art
Such a unit for storing data on picture images to be displayed in a video memory and reading the data from the video memory thereby to display the same on, e.g., a CRT display unit are well known by, for example, "Dedicated processor shrinks graphics system to 3 Chips" reported by Bob Williamson and Pete Rickert, Electronics Design, Aug. 4, 1983 and "VLSI CRT Controller cuts parts count of displays" reported by Richard Nesin, Electronics Design, Feb. 9, 1984.
FIG. 1 is a schematic block diagram showing a conventional video display control unit, and FIG. 2 is a definite block diagram of a video signal encoder as shown in FIG. 1. Referring to FIG. 1, description is now made on structure of the conventional video display control unit. The video display control unit includes a controller 1 for controlling the entire unit. Video information is displayed on a sequential scanning display unit 4, which displays picture images on a screen by continuously scanning video signals in the horizontal or vertical direction. Data on the video information to be displayed on the sequential scanning display unit 4 are stored in a video memory 5. The entire video display control unit is subjected to timing control by a clock and timing signal generator 26 which generates timing clock signals.
In order to continuously read the data stored in the video memory 5 in synchronization with scanning lines of the sequential scanning display unit 4, provided is a video memory address counter 6 which receives clock signals from the clock and timing signal generator 26 through a line 25. The video memory address counter 6 counts the clock signals, so as to generate its counter outputs on an address bus 7 as video memory address signals. The controller 1 outputs video memory address signals on an address bus 2 for reading and writing the data. An address multiplexer 8 receives selection signals from the clock and timing signal generator 26 through a line 24, thereby to switch the address buses 2 and 7 in response to the selection signals. A data bus interface 9 is connected to the controller 1 through an input/output data bus 3. The data bus interface 9 receives selection signals from the clock and timing signal generator 26 through the line 24, thereby to interface reading and writing of the data by the controller 1.
The video memory 5 is connected through a display data bus 10 to the data bus interface 9, an attribute code latch 11 and a character generator address latch 13. The display data bus 10 receives reading and writing data outputted from the controller 1 and reading data outputted from the video memory address counter 6.
The data outputted on the display data bus 10 include character generator address information indicating addresses of a character generator 16 in which character code patterns are recorded and attribute information indicating qualification codes for character symbols to be displayed. For example, when colors are added to the character symbols to be displayed, the attribute information includes codes indicating the colors. The attribute information outputted on the display data bus 10 is stored in the attribute code latch 11 on the basis of the timing of latch signals supplied from the clock and timing signal generator 26 through a line 22. The stored attribute information is supplied to a video signal encoder 18 through a bus 12.
On the other hand, the character generator address information outputted on the display data bus 10 is stored in the character generator address latch 13 at the timing of latch signals supplied from the clock and timing signal generator 26 through a line 23. The stored character generator address information is supplied through a bus 14 to the character generator 16, which further receives row addresses from the video memory address counter 6 through a bus 15 in its low-order addresses. The character generator 16 thus outputs the character information on a bus 17 in accordance with the character generator address information and the row addresses respectively received through the buses 14 and 15. The character information outputted on the bus 17 is supplied to the video signal encoder 18 in a parallel manner with the attribute information from the aforementioned attribute code latch 11.
The video signal encoder 18 composes video signals on the basis of the attribute information and the character information supplied in a parallel manner through the buses 12 and 17. In further detail, the attribute information and the character information are simultaneously latched by the video signal encoder 18 based on latch signals supplied from the clock and timing signal generator 26 through a line 20. The video signal encoder 18 composes the character information and the attribute information on the basis of video clock signals received from the clock and timing signal generator 26 through a line 21, thereby to convert the same into the video signals.
Referring now to FIG. 2, the video signal encoder 18 is further described in detail. The attribute information outputted on the bus 12 as shown in FIG. 1 is latched into an attribute latch 29 at the rise timing of the latch signals received through the line 20. The character information outputted on the bus 17 is supplied to a parallel/series converter 31 similarly at the rise timing of the latch signals. The parallel/series converter 31 converts the character information from parallel data to series data at the timing of the video clock signals outputted through the line 21. The series data are supplied to a multiplexer 33 through a line 32.
The outputs from the attribute latch 29 is divided into low-order bits 30a and high-order bits 30b. The divided low-order and high-order bits 30a and 30b can be defined to include, e.g., color information or color tone information. The multiplexer 33 selects the low-order bits 30a or the high-order bits 30b on the basis of the series data outputted on the line 32.
The video signals composed by the video signal encoder 18 are thus supplied to the sequential scanning display unit 4 through the line 19. The sequential scanning display unit 4 receives synchronization signals for controlling the timing of the scanning lines from a synchronizing signal generator 27 through a line 28. The synchronizing signal generator 27 generates the synchronizing signals on the basis of address counter clock signals received from the clock and timing signal generator 26 through the line 25. The sequential scanning display unit 4 receives the video signals and the synchronizing signals to display the picture images.
FIG. 3 is a timing chart showing the timing of principal signals in the conventional video display control unit as shown in FIG. 1, and is illustrative of states of the respective signals from data in addresses MA +2x and MA+2x+1 of video memory addresses to the video signals outputted on the line 19.
FIG. 4 illustrates relation between physical positions on the screen and addresses of the video memory specified by the video memory addresses for displaying horizontal x characters and characters of vertical y rows. In FIG. 4, two memory addresses are assigned to a character. For example, the address MA+2x is formed by addresses MA+2x and MA+2x+1. In other words, the character in the second stage MA +2x from above in the left-hand direction on the screen is stored in the addresses MA+2x and MA+2x+1 in the video memory 5. Even addresses are assigned to the character generator address information while odd addresses are assigned to the attribute information. Namely, contents of the even addresses indicate the sorts of the characters to be displayed, and contents of the odd addresses indicate the manners of qualification such as addition of colors to the characters to be displayed.
FIG. 5 shows an example of display of a character "A" in the position MA+2x on the screen by the character pattern of 8.times.8 dots for one character, with horizontal dots showing the list of the scanning lines. The character pattern "A" is stored in the character generator 16 by dot pattern information of 0 or 1, to be read on the basis of the timing of the scanning lines. The row addresses are indicative of the sequence of the scanning lines corresponding to the said one character, and 0 to 7 addresses are required for outputting the character as shown in FIG. 5 having the vertical height of 8 dots. Character information outputted from the character generator 16 in the case of the row address 0 is 00100000 in this example. The attribute information may be so defined as to indicate, e.g., red when the character pattern is 0 and green when the same is 1.
FIG. 6 is a timing chart showing the scanning timing in the case of FIG. 5. In FIG. 6, one row address corresponds to one scanning line, and video memory addresses for horizontally displayed characters (x characters) are changed in one scanning line interval to repeat such scanning eight times, thereby to complete display of x characters in the horizontal direction.
Description is now made on operations of the conventional display control unit with reference to FIGS. 1 to 6. In order to display the display example as shown in FIG. 5 on the sequential scanning display unit 4, the controller 1 writes the character address information in the character generator 16 storing the character to be displayed, e.g., "A" and the attribute information indicating the qualification codes therefor respectively in the addresses MA+2x and MA+2x+1 in the video memory 5 through the address bus 2 and the input/output data bus 3. This operation is performed by switching the address multiplexer 8 to the controller 1 side on the basis of selection signals outputted on the line 24 to specify prescribed addresses of the video memory 5 through the address bus 2, thereby to supply the video memory 5 with data from the input/output data bus 3 through the data bus interface 9 and the display data bus 10.
Although the video memory address signal outputted from the controller 1 and the video memory signal outputted from the video memory address counter 6 are described as equal for easy understanding of the prior art example, such equalization is not necessarily required.
The data thus written in the video memory 5 by the controller 1 are continuously read in synchronization with the screen scanning sequence at the timing as shown in FIG. 3 by the video memory address signal received from the video memory address counter 6 through the address bus 7. In FIG. 3, the character generator address signal in the address MA+2x is stored in the character generator address latch 13 at the rise timing of a latch signal on the line 23. On the basis of the output from the character generator address latch 13 supplied through the bus 14 and a row address from the video memory address counter 6 supplied through the bus 15, the character generator 16 outputs corresponding character information on the bus 17. On the other hand, the attribute information is read from the subsequent address MA+2x+1 of the video memory 5, to be latched into the attribute latch 11 at the rise timing of a latch signal outputted on the line 22. The latched attribute information is outputted on the bus 12.
The character information outputted on the bus 17 and the attribute information outputted on the bus 12 are written in a parallel manner in the video signal encoder 18 at the rise timing of a latch signal outputted on the line 20, to be converted into a video signal on the basis of the video clock signal supplied through the line 21. The video signal outputted on the line 19 as shown in FIG. 3 indicates the example for outputting the dots of the first row address for displaying the character "A" as shown in FIG. 5.
The conventional video display control unit is in the above described structure, and hence it is necessary to supply the character information and the attribute information in a parallel manner to the video signal encoder 18. Therefore, input signals to the video signal encoder 18 are increased, followed by increase in number of input pins of a package such as an integrated circuit for containing the video signal encoder 18, leading to increase of signal lines around the package.